Moore's law

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Moore's Law is a term attributed to Intel founder Gordon E. Moore who observed in 1965 that the number of transistors that could be purchased inexpensively and placed on an integrated-circuit doubles every year. He later revised this figure to every 2 years (1975).

The doubling period is often mistakenly reported as "18 months" or shorter,possibly due to being confused with estimates of overall computing power that DO double over that time period. However these estimates are based on additional factors such as increases in clock speed, size of cache memory or chip design. Moore's law is exclusively concerned with transistor density and nothing else.

The Future of Moore's Law

For almost as long as there's been Moore's Law there have been commentators predicting its demise due to the supposed limits of engineering having been reached. The ability to increase the number of transistors available is due to reducing transistor size rather than increasing the size of the integrated circuit. As of the first half of 2012 the smallest commercially available transistors on a microprocessor are 22 nanometers (around 1.5 Billion transistors per chip), their 1965 equivalent were 100 micrometers (100,000 nanometers) with 50 transistors per device.

However, it does appear that component size does have a limiting factor in the form of the Laws of Physics. On the smallest of scales electrons become "smeared" across time and space meaning that they can no longer remain contained within the boundaries of very small components which results in disastrous contamination of signal processing.

Carbon Nanotubes would appear to address this problem, but it may be some time before a method of mass fabricating Carbon Nanotube chips is possible and even if a method is discovered these components cannot be shrunk any further due to the fixed physical limits of their structure.

If shrinking components any further becomes impossible a new form of chip will be required to extend Moore's Law. One approach would involve chips that are "stacked" into 3-dimensional layers instead of the 2-dimensional designs of today. There are a number of engineering issues that need to be addressed in order for 3D chips to be viable, the most significant of which is the issue of heat dispersal. A number of chip manufacturers including IBM have announced plans to release "stacked" chip technology.

Whilst the International Technology Roadmap for Semiconductors has growth slowing at the end of 2013, Intel has publicly revealed it's own roadmap that projects a 5nm component scale by 2020.

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